Field of the Disclosure
The present disclosure relates generally to processing devices and, more particularly, to power management states in processing devices.
Description of the Related Art
Components in processing devices such as central processing units (CPUs), graphics processing units (GPUs), and accelerated processing units (APUs) can be operated in different power management states in which portions of the processing device can be deactivated or run at lower operating frequencies or voltages. For example, the power management states available to a component of a processing device may include an active state in which the component can be executing instructions and the component runs at a nominal operating frequency and operating voltage, an idle state in which the component does not execute instructions and may be run at a lower operating frequency or operating voltage, and a power-gated state in which the power supply is disconnected from the component, e.g., using a header transistor that interrupts the power supplied to the component when a power-gate signal is applied to a gate of the header transistor.
Processing devices can conserve power by transitioning one or more components from the active state to the idle state (i.e., idling one or more components) when there are no activities to be performed by the component(s) of the processing device. If the component is idle for a relatively long time, power supplied to the processing device may then be gated so that no current is supplied to the component, thereby reducing stand-by and leakage power consumption. For example, a processor core in a CPU can be power gated if the processor core has been idle for more than a predetermined time interval. However, transitioning between the power management states of a component of a processing device consumes system resources and therefore incurs costs. For example, transitioning into or out of the idle state from either the active state or the power-gated state imposes a performance cost due to the delay caused by the transition and may also impose an energy cost to perform operations prior to the transition. For another example, transitioning from an idle state to a power-gated state (i.e., power gating) requires flushing caches in the processor core, which consumes both time and power. Power gating also exacts a performance cost to return the processor core to an active state.
Conventional processing devices attempt to balance the benefits and costs of transitions between power management states using predetermined global time thresholds that are applied to all the components in the processing device. For example, a low-power state is more efficient than a higher power state only if a component's residency in the low-power state is sufficiently long that power savings associated with the low-power state exceed the power consumed during entry and exit transitions to and from the low-power state. Power management may therefore be disabled so that power management state transitions are disallowed when the overall (i.e., global) rate of transitions between the power management states caused by all processes being performed by a system rises above a predetermined threshold rate at which the costs of entering and exiting the low-power state are expected to exceed the power savings achieved while the component is in the low-power state. Power management may also be disabled when a global measure of the elapsed time between the transitions (such as an average of the elapsed times between all transitions performed by the system) is below a predetermined threshold interval. Since the precise performance costs of transitions between the power management states are not known at runtime, the thresholds are calibrated based on expected power savings and costs associated with the transition.